PRELIMINARY SPECIFICATIONS
———
PROGRAMMED DATA PROCESSOR
MODEL THREE
(PDP-3)
———
October, 1960
Digital Equipment Corporation
Maynard, Massachusetts
TABLE OF CONTENTS
INTRODUCTION 1 General Description 1 System Block Diagram 1 Electrical Description 4 Mechanical Description 4 Environmental Requirements 5 CENTRAL PROCESSOR 6 Operating Speeds 6 Instruction Format 6 Number System 7 Indexing 8 Indirect Addressing 8 Instruction List 9 Manual Controls 20 STORAGE 22 STANDARD INPUT-OUTPUT 23 Paper Tape Reader 23 Paper Tape Punch 24 Typewriter 24 OPTIONAL INPUT-OUTPUT 26 Sequence Break System 26 High Speed In-Out Channel 26 Magnetic Tape 27 CRT Display 33 Real Time Clock 33 Line Printer 34 UTILITY PROGRAMS 35 FRAP System 35 DECAL System 35 Floating Point Subroutines 36 Maintenance RoutinesINTRODUCTION
GENERAL DESCRIPTION
The DEC Programmed Data Processor Model Three (PDP-3) is a high performance, large scale digital computer featuring reliability in operation together with economy in initial cost, maintenance and use. This combination is achieved by the use of very fast, reliable, solid state circuits coupled with system design restraint. The simplicity of the system design excludes many marginal or superfluous features and thus their attendant cost and maintenance problems.
The average internal instruction execution rate is about 100,000 operations per second with a peak rate of 200,000 operations per second. This speed, together with its economy and reliability, recommends PDP-3 as an excellent instrument for complex real time control applications and as the center of a modern computing facility.
PDP-3 is a stored program, general purpose digital computer. It is a single address, single instruction machine operating in parallel on 36 bit numbers. It features multiple step indirect addressing and indexing of addresses. The main memory makes 511 registers available as index registers.
The main storage is coincident current magnetic core modules of 4096 words each. The computer has a built-in facility to address 8 modules and can be expanded to drive 64 modules. The memory has a cycle time of five microseconds.
SYSTEM BLOCK DIAGRAM
The flow of information between the various registers of PDP-3 is shown in the System Block Diagram (Fig. 1). There are four registers of 36 bit length. Their functions are described below.
Memory Buffer
The Memory Buffer is the central switching register. The word coming from or going to memory is retained in this register. In arithmetic operations it holds the addend, subtrahend, multiplicand, or divisor. The left 6 bits of this register communicate with the Instruction Register. The address portion of the Memory Buffer Register communicates with the Index Adder, the Memory Address Register, and the Program Counter. In certain instructions, the address portion of the control word does not refer to memory but specifies variations of an instruction, thus, the address portion of the Memory Buffer is connected to the Control Element.
Accumulator
The Accumulator is the main register of the Arithmetic Element. Sums and differences are formed in the Accumulator. At the completion of multiplication it holds the high order digits of the product. In division it initially contains the high order digits of the dividend and is left with the remainder.
The logical functions AND, inclusive OR, and exclusive OR, are formed in the Accumulator.
Carry Storage Register
The Carry Storage Register facilitates high-speed multiply and is properly part of the Accumulator.
In-Out Register
The In-Out Register is the main path of communication with external equipment. It is also part of the Arithmetic Element. In multiplication it ends with the low order digits of the product. In division it starts with the low order parts of the dividend and ends with the quotient.
The In-Out Register has a full set of shifting properties, (arithmetic and logical).
There are three registers of 15 bit length which deal exclusively with addresses. The design allows for expansion to 18 bits. These registers are:
Memory Addressing
The Memory Address Register holds the number of the memory location that is currently being interrogated. It receives this number from the Program Counter, the Index Adder or the Memory Buffer.
Program Counter
The Program Counter holds the memory location of the next instruction to be executed.
Index Adder
The Index Adder is a 15 bit ring accumulator. The sum of an instruction base address, Y, and the contents of an index register, C(x), are formed in this register. This register holds the previous content of the Program Counter in the "jump and save Program Counter," jps, instruction. The Index Adder also serves as the step counter in shift, multiply, and divide.
The Control Element contains two six bit registers and several miscellaneous flip-flops. The latter deal with indexing, indirect addressing, memory control, etc. The six bit registers are:
Instruction Register
The Instruction Register receives the first six bits of the Memory Buffer Register during the cycle which obtains the instruction from memory (cycle zero). This information is the primary input to the Control Element.
Program Flags
The six Program Flags act as convenient program switches. They are used to indicate separate states of a program. The program can set, clear, or sense the individual flip-flops. The program can also sense or make the state "All Flags ZERO." They can also be used to synchronize various input devices which occur at random times (see Input-Output, Typewriter Input).
Three toggle switch registers are connected to the Central Processor (see Manual Controls).
Test Address
The fifteen Test Address Switches are used to indicate start points and to select memory registers for manual examination or change.
Test Word
The thirty-six Test Word Switches indicate a new number for manual deposit into memory. They may also be used for insertion of constants while a program is operating by means of the operate instruction.
Sense Switches
The six Sense Switches allow the operator to manually select program options or cause a jump to another program in memory. The program can sense individual switches or the state "All Switches ZERO."
ELECTRICAL DESCRIPTION
The PDP-3 circuitry is the static type using saturating transistor flip-flops and, for the most part, transistor switch elements. The primary active elements are Micro-Alloy and Micro-Alloy-Diffused transistors. The flip-flops have built-in delay so that a logic net may be sampled and changed simultaneously.
Machine timing is performed by a delay line chain. Auxiliary delay line chains time the step counter instructions (multiply, divide, etc.). The machine is thus internally synchronous with step counter instructions being asynchronous. The
MECHANICAL DESCRIPTION
The PDP-3 consists of two mechanical assemblies, the Console and the Equipment Frame. Fig. 3 is a photograph of PDP-1 which is an 18 bit version of PDP-3.
Console
The Console is a desk approximately seven feet long. It contains the controls and indicators necessary for operation and maintenance of the machine. A cable connects the Console to the Equipment Frame.
Equipment Frame
The Equipment Frame is approximately six feet high and two feet deep. The length is a function of the amount of optional features included. The Central Processor requires a length of five and one half feet. The power cabinet is twenty-two inches long. A memory cabinet is thirty-two inches long and will hold three memory modules (12,288 words per cabinet). Memory cabinets may be added at any time.
Magnetic tape units require twenty-two inches per transport. A tape unit cabinet may be connected as an extension of the Equipment Frame or may be a free-standing frame.
ENVIRONMENTAL REQUIREMENTS
The PDP-3 requires no special room preparation. The computer will operate properly over the normal range of room temperature.
The Central Processor and memory together require thirty amperes of 110 volts single phase 60 cycle ac. Each inactive tape transport requires two amperes and the one active transport requires 10 amperes.
CENTRAL PROCESSOR
The Central Processor of PDP-3 contains the Control Element, the Memory Buffer Register, the Arithmetic Element, and the Memory Addressing Element. The Control Element governs the complete operation of the computer including memory timing, instruction performance, and the initiation of input-output commands. The Arithmetic Element, which includes the Accumulator, the In-Out Register, and the Carry Storage Register, performs the arithmetic operations. The Memory Addressing Element which includes the Index Adder, the Program Counter, and the Memory Address Register, performs address bookkeeping and modification.
OPERATING SPEEDS
Operating times of PDP-3 instructions are normally multiples of the memory cycle of 5 microseconds. Two cycle instructions refer twice to memory and thus require 10 microseconds for completion. Examples of this are add, subtract, deposit, load, etc. One cycle instructions do not refer to memory and require 5 microseconds. Examples of the latter are the jump instructions, the skip instructions, and the operate group. The operating times of variable cycle instructions depend upon the instruction. For example, the operating time for a shift or rotate instruction is 5 +0.2N microseconds, where N is the number of shifts performed. The operating times for multiply and divide are functions of the number of ones in the multiplier and in the quotient, respectively. Maximum time for multiply is 25 microseconds. This includes the time necessary to get the multiply instruction from memory. Divide takes 90 microseconds maximum.
In-Out Transfer instructions that do not include the optional wait function require 5 microseconds. If the in-out device requires a wait time for completion, the operating time depends upon the device being used.
If an instruction includes reference to an index register, an additional 5 microseconds is required. Each step of indirect addressing also requires an additional 5 microseconds.
INSTRUCTION FORMAT
The instructions for PDP-3 may be divided into three classes:
- Indexable memory instructions
- Non-indexable memory instructions
- Non-memory instructions.
The layout of the instruction word is shown in Fig. 2.
The octal digits 0 and 1 define the instruction code, thus, there are 64 possible instruction codes, not all of which are used. The first bit of octal digit 2 is the indirect address bit. If this bit is a ONE, indirect addressing occurs.
The index address, X, is in octal digits 3, 4, and 5. These digits address an index register for memory-type instructions. If these digits are all ZERO, indexing will not take place. In main memory, 511 of the registers can be used as automatic index registers.
The instruction base address, Y, is in octal digits 7 through 11. These digits are sufficient to address 32,768 words of memory. Octal digit 6 is reserved for further memory expansion. Space is available in the equipment frame for this expansion, should it prove desirable.
In those instructions which do not refer to memory, the memory address digits, Y, and in some cases the index address digits also, are used to specify the variations in any group of instructions. An example of this is in the shift and rotate instructions in which the memory address digits determine the number of shifts.
NUMBER SYSTEM
The PDP-3 is a "fixed" point machine using binary arithmetic. Negative numbers are represented as the 1's complement of the positive numbers. Bit 0 is the sign bit which is ZERO for positive numbers. Bits 1 to 35 are magnitude bits with bit 1 being the most significant and bit 35 being the least significant.
The actual position of the binary point may be arbitrarily assigned to best suit the problem in hand. Two common conventions in the placement of the binary point are:
- The binary point is to the right of the least significant digit, thus, numbers represent integers.
- The binary point is to the right of the sign digit, thus the numbers represent a fraction which lies between ±1.
The conversion of decimal numbers into the binary system for use by the machine may be performed automatically by subroutines. Similarly the output conversion of binary numbers into decimals is done by subroutine. Operations for floating point numbers are handled by programming. The utility program system provides for automatic insertion of the routines required to perform floating point operations and number base conversion (see Utility Programs).
INDEXING
In PDP-3, 511 registers of the main magnetic core memory are available for use as automatic index registers. Their addresses are specified by octal digits 3 to 5 of the instruction word. These registers are memory locations 001-777 (octal). Address 000 specifies that no index register is to be used with the instructions. The contents of octal digits 7 through 11 of the selected index register are added to the unmodified address (octal digits 7 through 11 of the instruction).
This sum is used to locate the operand. The addition is done in the Index Adder which is a 15 bit 1's complement adder. The contents of the Accumulator and the In-Out Register are unaffected
Three special instructions snx, spx and lir, are available to facilitate resetting, advancing, and sampling of the index registers. Since the index registers are normal memory registers, their contents can also be manipulated by the standard computer instructions.
INDIRECT ADDRESSING
An instruction which is to use an indirect address will have a ONE in bit six of the instruction word. The original address, Y, of the instruction will not be used to locate the operand of the instruction, as is the normal case. Instead, it is used to locate a memory register whose contents in octal digits 7 through 11 will be used as the address of the original instruction. This new address is known as the indirect address for the instruction and will be used to locate the operand. If the memory register containing the indirect address also has a 1 in bit six, the indirect addressing procedure is repeated again and a third address is located. There is no limit to the number of times this process can be repeated.
Index registers may be used in conjunction with indirect addressing. In this case, the address after being modified by the selected index register is used to locate the indirect address.
The indirect address can be acted on by an index register and deferred again if desired. Each use of an index register or an indirect address extends the operating time of the original instruction by 5 microseconds.
INSTRUCTION LIST
This list includes the title of the instruction, the normal execution time of the instruction, i.e., the time with no indexing and no deferring, the mnemonic code of the instruction, and the operation code number. The notation used requires the following definitions. The contents of a register Q are indicated as C(Q). The address portion of the instruction is indicated by Y. The index register address of an instruction is indicated by x. The effective address of an operand is indicated by Z. Z may be equal to Y or it may be Y as modified by deferring or by indexing.
Indexable Memory Instructions
Arithmetic Instructions
Add(10 usec.)
add x Y Operation Code 40
The new C(AC) are the sum of C(Z) and the original C(AC). The C(Z) are unchanged. The addition is performed with 1's complement arithmetic.
If the sum exceeds the capacity of the Accumulator Register, the overflow flip-flop will be set (see Skip Group instructions).
Subtract(10 usec.)
sub x Y Operation Code 42
The new C(AC) are the original C(AC) minus the C(Z). The C(Z) are unchanged. The subtraction is performed using 1's complement arithmetic.
If the difference exceeds the capacity of the Accumulator, the overflow flip-flop will be set (see Skip Group instructions).
Multiply(approximately 25 usec.)
mul x Y Operation Code 54
The C(AC) are multiplied by the C(Z). The most significant digits of the product are left in the Accumulator and the least significant digits in the In-Out Register. The previous C(AC) are lost.
Divide(approximately 90 usec.)
div x Y Operation Code 56
The Accumulator and the In-Out Register together form a 70 bit dividend. The high order part of the dividend is in the Accumulator. The low order part of the dividend is in the In-Out Register. The divisor is (Z).
Upon completion of the division, the quotient is in the In-Out Register. The remainder is in the Accumulator. The sign of the remainder is the same as the sign of the dividend. If the dividend is larger than C(Z), the overflow flip-flop will be set and the division will not take place.
Logical Instructions
Logical AND(10 usec.)
and x Y Operation Code 02
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the logical AND. The result is left in the Accumulator. The C(Z) are unaffected by this instruction.
Logical AND Function Table
AC Bit C(Z) Bit Result 0 0 0 0 1 0 1 0 0 1 1 1Exclusive OR(10 usec.)
xor x Y Operation Code 06
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the exclusive OR. The result is left in the Accumulator. The C(Z) are unaffected by this order.
Exclusive OR Table
AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 0Inclusive OR(10 usec.)
ior x Y Operation Code 04
The bits of C(Z) operate on the corresponding bits of the Accumulator to form the inclusive OR. The result is left in the Accumulator. The C(Z) are unaffected by this order.
Inclusive OR Table
AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 1General Instructions
Load Accumulator(10 usec.)
lac x Y Operation Code 20
The C(Z) are placed in the Accumulator. The C(Z) are unchanged. The original C(Z) are lost.
dac x Y Operation Code 24
The C(AC) replace the C(Z) in the memory. The C(AC) are left unchanged by this instruction. The original C(Z) are lost.
Deposit Address Part(10 usec.)
dap x Y Operation Code 26
Octal digits 6 through 11 of the Accumulator replace the corresponding digits of memory register Z.
C(AC) are unchanged as are the contents of octal digits 0 through 5 of Z. The original contents of octal digits 6 through 11 of Z are lost.
Deposit Instruction Part(10 usec.)
dip x Y Operation Code 30
Octal digits 0 through 5 of the Accumulator replace the corresponding digits of memory register Z. The Accumulator is unchanged as are digits 6 through 11 of Z. The original contents of octal digits 0 through 5 of Z are lost.
Load In-Out Register(10 usec.)
lio x Y Operation Code 22
The C(Z) are placed in the In-Out Register. C(Z) are unchanged. The original C(IO) are lost.
Deposit In-Out Register(10 usec.)
dio x Y Operation Code 32
The C(IO) replace the C(Z) in memory. The C(IO) are unaffected by this instruction. The original C(Z) are lost.
Jump(5 usec.)
jmp x Y Operation Code 60
The Program Counter is reset to address Z. The next instruction that will be executed will be taken from memory register Z. The original contents of the Program Counter are lost.
Jump and Save Program Counter(5 usec.)
jsp x Y Operation Code 62
The contents of the Program Counter are transferred to the Index Adder. When the transfer takes place, the Program Counter holds the address of the instruction following the jsp. The Program Counter is then reset to address Z. The next instruction that will be executed will be taken from memory register Z.
Skip if Accumulator and Z differ(10 usec.)
sad x Y Operation Code 50
The C(Z) are compared with the C(AC). If the two numbers are different, the Program Counter is indexed one extra position and the next instruction in the sequence is skipped. The C(AC) and the C(Z) are unaffected by this operation.
Skip if Accumulator and Z are the same(10 usec.)
sas x Y Operation Code 52
The C(Z) are compared with C(AC). If the two numbers are identical, the Program Counter is indexed one extra position and the next instruction in the sequence is skipped. The C(AC) and C(Z) are unaffected by this operation.
Non-Indexable Memory Instructions
These instructions have the same word format as the indexable instructions. Since they operate on the index register location, x, they cannot be indexed.
Skip on Negative index(10 usec.)
snx x Y Operation Code 46
The number in octal digits 7 through 11 of the instruction word is added to the C(x). This addition is done in the 15 bit Index Adder using 1's complement arithmetic. If, after the addition, the sum is negative, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped. The contents of octal digits 0-5 of the index register location are unaffected by this instruction.
Skip on Positive index(10 usec.)
spx x Y Operation Code 44
The number in octal digits 7 through 11 of the instruction word is added to the C(x). This addition is done in the 15 bit Index Adder using 1's complement arithmetic.
If, after the addition, the sum is positive, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped. The contents of octal digits 0-5 of the index register location are unaffected by this instruction.
Load Index Register(10 usec.)
lir x Y Operation Code 14
The octal digits 7 through 11 (Y) of the instruction will replace the corresponding digits of the memory register specified by x. Octal digit 6 of the memory register will be left clear. Digits 0-5 of the memory register are unchanged.
Deposit Index Adder(10 usec.)
dia x Y Operation Code 16
The C(IA) replace the octal digits 7 through 11 of memory location Y. Octal digit 6 of Y is cleared. Digits 0 through 5 of Y are left unchanged. The x portion of the instruction is ignored.
Non-Memory Instructions
Rotate and Shift Group
This group of instructions will rotate or shift the Accumulator and/or the In-Out Register. When the two registers operate combined, the In-Out Register is considered to be a 36 bit magnitude extension of the right end of the Accumulator.
Rotate is a non-arithmetic cyclic shift. That is, the two ends of the register are logically tied together and information is rotated as though the register were a ring.
Shift is an arithmetic operation and is in effect multiplication of the number in the register by 2+N, where N is the number of shifts. Shift or rotate instructions involving more than 33 steps can be used for simulating time delays. 36 rotate steps of the Accumulator will return all information to its original position.
Rotate Accumulator Right(13 usec. maximum for 36 shifts)
rar N Operation Code 671
This instruction will rotate the bits of the Accumulator right N positions, where N is octal digits 7-11 of the instructions word.
Rotate Accumulator Left(13 usec. maximum for 36 shifts)
ral N Operation Code 661
This instruction will rotate the bits of the Accumulator left N Positions, where N is octal digits 7-11 of the instruction word.
Shift Accumulator Right(13 usec. maximum for 36 shifts)
sar N Operation Code 675
This instruction will shift the contents of the Accumulator right N positions, where N is octal digits 7-11 of the instruction word.
Shift Accumulator Left(13 usec. maximum for 36 shifts)
sal N Operation Code 665
This instruction will shift the contents of the Accumulator left N positions, where N is octal digits 7-11 of the instruction word.
Rotate In-Out Register Right(13 usec. maximum for 36 shifts)
rir N Operation Code 672
This instruction will rotate the bits of the In-Out Register right N positions, where N is octal digits 7-11 of the instruction word.
Rotate In-Out Register Left(13 usec. maximum for 36 shifts)
ril N Operation Code 662
This instruction will rotate the bits of the In-Out Register left N positions, where N is octal digits 7-11 of the instruction word.
Shift In-Out Register Right(13
sir N Operation Code 676
This instruction will shift the contents of the In-Out Register right N positions, where N is octal digits 7-11 of the instruction word.
Shift In-Out Register Left(13 usec. maximum for 36 shifts)
sil N Operation Code 666
This instruction will shift the contents of the In-Out Register left N positions, where N is octal digits 7-11 of the instruction word.
Rotate AC and IO Right(13 usec. maximum for 36 shifts)
rcr N Operation Code 673
This instruction will rotate the bits of the combined register right in a single ring N positions, where N is octal digits 7-11 of the instruction word.
Rotate AC and IO Left(13 usec. maximum for 36 shifts)
rcl N Operation Code 663
This instruction will rotate the bits of the combined register left in a single ring N position, where N is octal digits 7-11 of the instruction word.
Shift AC and IO Right(13 usec. maximum for 36 shifts)
scr N Operation Code 677
This instruction will shift the contents of the combined register right N positions, where N is octal digits 7-11 of the instruction word.
Shift AC and IO Left(13 usec. maximum for 36 shifts)
scl N Operation Code 667
This instruction will shift the contents of the combined registers left N positions, where N is octal digits 7-11 of the instruction word.
Skip Group(5 usec.)
skp Y Operation Code 64
This group of instructions senses the state of various flip-flops and switches in the machine. It does not require any reference to memory. The address portion of the instruction selects the particular function to be sensed. All members of this group have the same operation code.
Skip on ZERO Accumulator(5 usec.)
sza Address 100
If the Accumulator is equal to plus ZERO (all bits are ZERO) the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on Plus Accumulator(5 usec.)
spa Address 200
If the sign bit of the Accumulator is ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on Minus Accumulator(5 usec.)
sma Address 400
If the sign bit of the Accumulator is ONE, the Program Counter is advanced one extra position and the next instruction in the sequence is skipped.
Skip on ZERO Overflow(5 usec.)
szo Address 1000
If the overflow flip-flop is a ZERO the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. The overflow flip-flop is cleared by this instruction. This flip-flop is set by addition, subtraction, or division that exceeds the capacity of the Accumulator. The overflow flip-flop is not cleared by arithmetic operations which do not cause an overflow. Thus, a whole series of arithmetic operations may be checked for correctness by a single szo. The overflow flip-flop is cleared by the "Start" Switch.
Skip on Plus In-Out Register(5 usec.)
spi Address 2000
If the sign digit of the In-Out Register is ZERO the Program Counter is indexed one extra position and the next instruction in the sequence is skipped.
Skip on ZERO Switch(5 usec.)
szs Addresses 10, 20, ... 70
If the selected Sense Switch is ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 10 senses the position of Sense Switch 1, Address 20 Switch 2, etc. Address 70 senses all the switches. If 70 is selected all 6 switches must be ZERO to cause the skip to occur.
Skip on ZERO Program Flag(5 usec.)
szf Addresses 0 to 7 inclusive
If the selected program flag is a ZERO, the Program Counter is advanced one extra position and the next instruction in the sequence will be skipped. Address 0 is no selection. Address 1 selects program flag one, etc. Address 7 selects all programs flags. All flags must be ZERO to cause the skip.
The instructions in the One Cycle Skip group may be combined to form the inclusive OR of the separate skips. Thus, if address 3000 is selected, the skip would occur if the overflow flip-flop equals ZERO or if the In-Out Register is positive. The combined instruction would still take 5 microseconds.
Operate Group(5 usec.)
opr Y Operation Code 76
This instruction group performs miscellaneous operations on various Central Processor Registers. The address portion of the instruction specifies the action to be performed.